GAA; CIM architecture; MIT’s AI Chip; hybrid bonding; wafer defects; quantum; DL for Materials; electro-optics modulator; wide bandgap; design hiding schemes
New technical papers added to Semiconductor Engineering’s library this week.
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Suppliers are investing new 300mm capacity, but it’s probably not enough. And despite burgeoning 200mm demand, only Okmetic and new players in China are adding capacity.
100% inspection, more data, and traceability will reduce assembly defects plaguing automotive customer returns.
Increased transistor density and utilization are creating memory performance issues.
Tech and auto giants are putting even more pressure on the semiconductor labor market. Some say it could be just what the industry needs.
There are at least three architectural layers to processor design, each of which plays a significant role.
Interest in this particular ISA is expanding, but the growth of other open-source hardware is less certain.
Nanosheets are likeliest option throughout this decade, with CFETs and other exotic structures possible after that.
Suppliers are investing new 300mm capacity, but it’s probably not enough. And despite burgeoning 200mm demand, only Okmetic and new players in China are adding capacity.
100% inspection, more data, and traceability will reduce assembly defects plaguing automotive customer returns.
From low resistance vias to buried power rails, it takes multiple strategies to usher in 2nm chips.
Some of the less common considerations for assessing the suitability of a system for high-performance workloads.
Manufacturing 3D structures will require atomic-level control of what’s removed and what stays on a wafer.
Different interconnect standards and packaging options being readied for mass chiplet adoption.
