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In circumstances that forced the postponement of its live conferences, seminars, and workshops, EIPC has continued to provide its platform for the exchange and dissemination of market knowledge and technical information to the European interconnection and packaging industry. It’s over a year since EIPC launched its remarkably popular series of Technical Snapshot webinars, and they continue to be timely and topical. October 22 brought the 12th in the sequence, introduced and moderated by Martyn Gaudion, EIPC board member and CEO of Polar Instruments.
The principal driver of printed circuit layout rules is component packaging technology. What does the future hold? Jan Vardaman, president and founder of TechSearch International, recognised as a leading analyst in the field of advanced semiconductor packaging, gave a comprehensive assessment in her presentation, “Electronic Industry Growth Markets: Package Choices, Challenges, and Trends.”
She observed that the electronics industry is seeing continuing recovery in demand although supply in some sectors, particularly automotive, are currently hampered by semiconductor shortages and supply-chain disruption. 5G and millimetre-wave rollouts, and the consequent demand for small-cell infrastructure are driving the demand for complex system-in-package and antenna-in-package modules and an unprecedented era of change is envisaged for packaging.
The economic advantages of pure silicon scaling are gone, but heterogeneous integration presents opportunities to regain some economic benefits by the use of silicon interposers, fan-out-on-substrate, chiplets, and variations of 3D stacking. Heterogeneous integration offers improved signal and power integrity, lower inductance and thermal resistance as well as form-factor advantages but co-design of silicon and package are essential, thermal issues must be addressed, and material selection is important.
In addition to cost benefits, the functional advantages of this new era of high-performance packaging, with the adoption of silicon interposer, 3D stacking, and high-density fan-out technologies will include low latency, bandwidth and data-rate increases, better power efficiency and improved power delivery as well as increases in routing and input-output density.
Vardaman listed examples of many different packaging options, mostly proprietary, and described several instances of silicon interposers used to provide high-density connection between logic and high-bandwidth memory stacks, already a well-established technique. She also showed proprietary examples of fan-out-chip-on-substrate, silicon-wafer-integrated-fan-out-technology, and embedded-multi-die-interconnect bridge solutions.
Chiplets are featured in the multi-chip architecture revolution and are predicted to become key enablers during the next 10 to 20 years as die sizes continued to increase over time for server central processing units and graphics processing units. Future performance will demand more transistors, while the industry needs a new, more economical approach. Smart packaging, including heterogeneous integration and chiplets, provide the answer.
A chiplet was defined as an integrated circuit block specifically designed to work with other chiplets to form a larger more complex system that often made use of reusable intellectual-property blocks. It differs from system-in-package or traditional multi-chip-modules in that it is a new design, not just a combination of different off-the-shelf chips. Vardaman stressed that the chiplet is not so much a package but a design philosophy that requires the industry to think about chip design in a new way and change from silicon-centric thinking to system-level planning and co-design of integrated circuit and package. She again showed many proprietary examples.
Which one to choose of all these package options? Her list of factors to be considered included routing density requirements, power efficiency and power delivery, maturity of the technology, supply chain, thermal performance needs, test considerations, relative costs versus alternatives, and product life and reliability requirements.
This was an enormous amount of information and an opportunity for the PCB fabricators in the audience to gain some understanding of the internal complexity of the packages that will populate their product and whose geometries and characteristics will influence its design rules and material requirements.
EIPC president Alun Morgan, technology ambassador for Ventec International Group, modestly assumed responsibility for re-focusing attention away from the esoteric topic of high-end packaging technology toward the relatively prosaic subject of low-loss materials. In the event, his presentation, “We need to talk about PTFE,” was a most informative lesson in understandable materials science, delivered in Morgan’s clear and logical style.
He explained the mechanism of dielectric loss in terms of the displacement of positive and negative charges within an insulating material relative to an applied electric field, resulting in polarisation that caused part of the applied field to be lost. The amount of polarisation that could occur depended on the symmetry of the molecular structure and, although the overall charge was zero, the degree to which positive and negative charges did not completely overlap could be quantified in terms of a dipole moment. His example of the behaviour exhibited by water molecules in a microwave oven demonstrated the effect.
The inherent dissipation by a dielectric in an applied electric field is quantified as its loss tangent, alternatively its loss factor, dissipation factor, dielectric loss, loss angle or tan delta. Morgan’s chart of loss factors at 1GHz showed a series of values from air at zero through alumina at 0.0002, water at 0.06, E-glass at 0.0012, NE-glass at 0.0006, standard FR-4 at 0.015, phenolic cured FR4 at 0.020, ceramic filled low loss substrate at 0.003 and PTFE-based PCB substrate at 0.001. He commented that PTFE and highly-ceramic-filled variants were becoming the materials of choice for designers with ultra-low-loss requirements.
Ho summarised the physical properties of PTFE as a highly crystalline thermoplastic polymer, without a glass transition temperature, a molecular structure composed of stiff carbon backbones with fluorine atoms arranged in spirals around them. Its thermodynamics give it a high melting point and very little flow in the molten state. Consequently, processing is achieved by sintering. Its coefficient of thermal expansion can be closely controlled by the addition of a micro-dispersed filler. It is almost inert chemically, and its properties are consistent over time. Morgan added the further observation that its non-stick properties are such that it defeated the cling-on capability of the gecko!
He described equipment for measuring dielectric constant and dissipation factor by transmission-line and resonator methods and mentioned proprietary techniques for measuring insertion loss before taking examples from Ventec’s R&D Roadmap for PTFE materials to illustrate the properties of materials for both low and high dielectric constant applications. High dielectric constant materials are required for certain designs; Dk values as high as 10 can be achieved by the use of fillers or could be as low as 3. Many of the materials have no glass reinforcement; some have random-glass fibre. All are based on PTFE and most include a filler system to modify their mechanical properties.
The market for PTFE materials, which had been niche and specialist a few years ago, has grown massively, especially with the advent of 5G, low-noise amplifiers and antennas.
Taking as his example one of the materials from the list, a ceramic-filled PTFE composite without woven glass reinforcement, Morgan delved into its properties. It exhibits low dielectric loss and minimal signal distortion in microwave applications, with very smooth copper for minimising insertion loss through skin effects at higher frequencies. Thermal expansion coefficients are low in all three axes and thickness and dielectric constant are controlled within close tolerances. Typical applications are 77-81GHz automotive radar, traffic detection radar, low noise power amplifiers and antennas for wireless and satellite communications. Moisture absorption, a very significant parameter when considering loss, is measured at only about 0.04%, whereas a typical value for FR-4 is around 0.25% and polyimides could be as high as 1%.
Having mentioned copper and skin effects, he reviewed the available low-profile foil options, and commented that whereas electrodeposited foils had been predominant, rolled-annealed foil is now finding applications in very-low-loss materials.
Morgan concluded with a few notes on processability, commenting that through-holes can be satisfactorily drilled mechanically and plated, and laser-drilled blind vias are practicable.
His presentation went a long way toward providing “all you wanted to know about PTFE but were afraid to ask ….” although there was plenty of scope in the Q&A session that followed.
In wrapping-up the proceedings, Gaudion was delighted to announce that EIPC would be at the productronica exhibition in November, and all were welcome to visit—an opportunity to meet face-to-face after all this time. Indeed, the first live EIPC conference is planned for February 10 in Frankfurt. Look out for further announcements.
Pete Starkey is an I-Connect007 technical editor.
In circumstances that forced the postponement of its live conferences, seminars, and workshops, EIPC has continued to provide its platform for the exchange and dissemination of market knowledge and technical information to the European interconnection and packaging industry. It’s over a year since EIPC launched its remarkably popular series of Technical Snapshot webinars, and they continue to be timely and topical. October 22 brought the 12th in the sequence, introduced and moderated by Martyn Gaudion, EIPC board member and CEO of Polar Instruments.
The principal driver of printed circuit layout rules is component packaging technology. What does the future hold? Jan Vardaman, president and founder of TechSearch International, recognised as a leading analyst in the field of advanced semiconductor packaging, gave a comprehensive assessment in her presentation, “Electronic Industry Growth Markets: Package Choices, Challenges, and Trends.”
She observed that the electronics industry is seeing continuing recovery in demand although supply in some sectors, particularly automotive, are currently hampered by semiconductor shortages and supply-chain disruption. 5G and millimetre-wave rollouts, and the consequent demand for small-cell infrastructure are driving the demand for complex system-in-package and antenna-in-package modules and an unprecedented era of change is envisaged for packaging.
The economic advantages of pure silicon scaling are gone, but heterogeneous integration presents opportunities to regain some economic benefits by the use of silicon interposers, fan-out-on-substrate, chiplets, and variations of 3D stacking. Heterogeneous integration offers improved signal and power integrity, lower inductance and thermal resistance as well as form-factor advantages but co-design of silicon and package are essential, thermal issues must be addressed, and material selection is important.
In addition to cost benefits, the functional advantages of this new era of high-performance packaging, with the adoption of silicon interposer, 3D stacking, and high-density fan-out technologies will include low latency, bandwidth and data-rate increases, better power efficiency and improved power delivery as well as increases in routing and input-output density.
Vardaman listed examples of many different packaging options, mostly proprietary, and described several instances of silicon interposers used to provide high-density connection between logic and high-bandwidth memory stacks, already a well-established technique. She also showed proprietary examples of fan-out-chip-on-substrate, silicon-wafer-integrated-fan-out-technology, and embedded-multi-die-interconnect bridge solutions.
Chiplets are featured in the multi-chip architecture revolution and are predicted to become key enablers during the next 10 to 20 years as die sizes continued to increase over time for server central processing units and graphics processing units. Future performance will demand more transistors, while the industry needs a new, more economical approach. Smart packaging, including heterogeneous integration and chiplets, provide the answer.
A chiplet was defined as an integrated circuit block specifically designed to work with other chiplets to form a larger more complex system that often made use of reusable intellectual-property blocks. It differs from system-in-package or traditional multi-chip-modules in that it is a new design, not just a combination of different off-the-shelf chips. Vardaman stressed that the chiplet is not so much a package but a design philosophy that requires the industry to think about chip design in a new way and change from silicon-centric thinking to system-level planning and co-design of integrated circuit and package. She again showed many proprietary examples.
Which one to choose of all these package options? Her list of factors to be considered included routing density requirements, power efficiency and power delivery, maturity of the technology, supply chain, thermal performance needs, test considerations, relative costs versus alternatives, and product life and reliability requirements.
This was an enormous amount of information and an opportunity for the PCB fabricators in the audience to gain some understanding of the internal complexity of the packages that will populate their product and whose geometries and characteristics will influence its design rules and material requirements.
EIPC president Alun Morgan, technology ambassador for Ventec International Group, modestly assumed responsibility for re-focusing attention away from the esoteric topic of high-end packaging technology toward the relatively prosaic subject of low-loss materials. In the event, his presentation, “We need to talk about PTFE,” was a most informative lesson in understandable materials science, delivered in Morgan’s clear and logical style.
He explained the mechanism of dielectric loss in terms of the displacement of positive and negative charges within an insulating material relative to an applied electric field, resulting in polarisation that caused part of the applied field to be lost. The amount of polarisation that could occur depended on the symmetry of the molecular structure and, although the overall charge was zero, the degree to which positive and negative charges did not completely overlap could be quantified in terms of a dipole moment. His example of the behaviour exhibited by water molecules in a microwave oven demonstrated the effect.
The inherent dissipation by a dielectric in an applied electric field is quantified as its loss tangent, alternatively its loss factor, dissipation factor, dielectric loss, loss angle or tan delta. Morgan’s chart of loss factors at 1GHz showed a series of values from air at zero through alumina at 0.0002, water at 0.06, E-glass at 0.0012, NE-glass at 0.0006, standard FR-4 at 0.015, phenolic cured FR4 at 0.020, ceramic filled low loss substrate at 0.003 and PTFE-based PCB substrate at 0.001. He commented that PTFE and highly-ceramic-filled variants were becoming the materials of choice for designers with ultra-low-loss requirements.
Ho summarised the physical properties of PTFE as a highly crystalline thermoplastic polymer, without a glass transition temperature, a molecular structure composed of stiff carbon backbones with fluorine atoms arranged in spirals around them. Its thermodynamics give it a high melting point and very little flow in the molten state. Consequently, processing is achieved by sintering. Its coefficient of thermal expansion can be closely controlled by the addition of a micro-dispersed filler. It is almost inert chemically, and its properties are consistent over time. Morgan added the further observation that its non-stick properties are such that it defeated the cling-on capability of the gecko!
He described equipment for measuring dielectric constant and dissipation factor by transmission-line and resonator methods and mentioned proprietary techniques for measuring insertion loss before taking examples from Ventec’s R&D Roadmap for PTFE materials to illustrate the properties of materials for both low and high dielectric constant applications. High dielectric constant materials are required for certain designs; Dk values as high as 10 can be achieved by the use of fillers or could be as low as 3. Many of the materials have no glass reinforcement; some have random-glass fibre. All are based on PTFE and most include a filler system to modify their mechanical properties.
The market for PTFE materials, which had been niche and specialist a few years ago, has grown massively, especially with the advent of 5G, low-noise amplifiers and antennas.
Taking as his example one of the materials from the list, a ceramic-filled PTFE composite without woven glass reinforcement, Morgan delved into its properties. It exhibits low dielectric loss and minimal signal distortion in microwave applications, with very smooth copper for minimising insertion loss through skin effects at higher frequencies. Thermal expansion coefficients are low in all three axes and thickness and dielectric constant are controlled within close tolerances. Typical applications are 77-81GHz automotive radar, traffic detection radar, low noise power amplifiers and antennas for wireless and satellite communications. Moisture absorption, a very significant parameter when considering loss, is measured at only about 0.04%, whereas a typical value for FR-4 is around 0.25% and polyimides could be as high as 1%.
Having mentioned copper and skin effects, he reviewed the available low-profile foil options, and commented that whereas electrodeposited foils had been predominant, rolled-annealed foil is now finding applications in very-low-loss materials.
Morgan concluded with a few notes on processability, commenting that through-holes can be satisfactorily drilled mechanically and plated, and laser-drilled blind vias are practicable.
His presentation went a long way toward providing “all you wanted to know about PTFE but were afraid to ask ….” although there was plenty of scope in the Q&A session that followed.
In wrapping-up the proceedings, Gaudion was delighted to announce that EIPC would be at the productronica exhibition in November, and all were welcome to visit—an opportunity to meet face-to-face after all this time. Indeed, the first live EIPC conference is planned for February 10 in Frankfurt. Look out for further announcements.
Pete Starkey is an I-Connect007 technical editor.
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